
COMMERCIALTEMPERATURERANGE
2
IDTCV115-2
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PIN CONFIGURATION
SSOP
TOP VIEW
HW FREQUENCY SELECTION TABLE
FSC, B, A
CPU
SRC4_SATA
SRC[3:1], SCR[7:5]
PCI
USB
DOT
REF
101
100
33.3
48
96
14.318
001
133
100
33.3
48
96
14.318
011
166
100
33.3
48
96
14.318
010
200
100
33.3
48
96
14.318
000
266
100
33.3
48
96
14.318
100
333
100
33.3
48
96
14.318
110
400
100
33.3
48
96
14.318
111
Reserve
100
33.3
48
96
14.318
TEST MODE SELECT(1)
If TEST_SEL sampled above 2V at VTT_PWRGD active LOW
Pin38
(test_mode)
CPU
SRC
PCI/F
REF
DOT96
USB
1
REF/N
REF
REF/N
0
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N,
ITP_EN
pin 35
pin 36
1
CPUC2_ITP
CPUT_ITP
0
SRCC7
SRCT7
ITP_EN
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI1
PCI0
FS_A(REF1/PCI5)
FS_C/REF0
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SCL
SDA
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
Reset#
CPU2_ITP/SRCT7
CPU2_ITP/SRCC7
VDD_SRC
SRCC6
SRCT5
SRCC5
VSS_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD_PCI
VSS_PCI
PCI2
PCI3
PCI4/Turbo1
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
VTT_PWRGD/PWRDWN#
VDD_48
FS_B/USB48MHz
VSS_48
DOT_96
DOT_96#
PCIF2
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRCT4_SATA
VDD_SRC
SRCT6
VSS
VSS_GND
SRCC4_SATA
VDD_suspend
VSS_CPU
Turbo2
(1)
(2)
(4)
(2)
(3)
NOTES:
1. After power on, pin 5 is tristate (see Byte 30 and Byte 2).
2. ~ 130K
Ω internal pull-up.
3. After power on, REF1/PCI5 is tristate (see Byte 1).
4. Disabled at power on.